The International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2008)
ページ
292 - 295
発行年
2008-01-01
出版者
IEEE = Institute of Electrical and Electronics Engineers
抄録
This paper presents an computationally ef cient implementation of sparse-tap FIR adaptive lters with tapposition control on Intel IA-32 processors with single-instruction multiple-data (SIMD) capability. In order to overcome randomorder memory access which prevents a ectorization, a blockbased processing and a re-ordering buffer are introduced. A dynamic register allocation and the use of memory-to-register operations help the maximization of the loop-unrolling level. Up to 66percent speedup is achieved.
内容記述
Organized by the Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technology Association (ECTI) Co-organized by GCEO-NGIT, Hokkaido University Technical sponsored by IEEE Circuits and Systems Society In cooperation with the Institute of Electronics, Information and Communication Engineering (IEICE)
Computationally efficient implementation of sarse-tap FIR adaptive filters with tap-position control on intel IA-32 processors
TE-PR-HIRANO-A-292.pdf
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