WEKO3
インデックスリンク
アイテム
{"_buckets": {"deposit": "e1a327dd-d226-4cba-b946-759ef7d92b8b"}, "_deposit": {"created_by": 3, "id": "8419", "owners": [3], "pid": {"revision_id": 0, "type": "depid", "value": "8419"}, "status": "published"}, "_oai": {"id": "oai:kanazawa-u.repo.nii.ac.jp:00008419", "sets": ["4187"]}, "author_link": ["535", "11797", "2278", "11796", "11794", "11795", "10707", "2717"], "item_4_biblio_info_8": {"attribute_name": "書誌情報", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2011-01-01", "bibliographicIssueDateType": "Issued"}, "bibliographicPageStart": "6026600", "bibliographic_titles": [{"bibliographic_title": "Midwest Symposium on Circuits and Systems"}]}]}, "item_4_creator_33": {"attribute_name": "著者別表示", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "深山, 正幸 "}], "nameIdentifiers": [{"nameIdentifier": "2278", "nameIdentifierScheme": "WEKO"}, {"nameIdentifier": "30324106", "nameIdentifierScheme": "e-Rad", "nameIdentifierURI": "https://kaken.nii.ac.jp/ja/search/?qm=30324106"}]}, {"creatorNames": [{"creatorName": "松田, 吉雄 "}], "nameIdentifiers": [{"nameIdentifier": "2717", "nameIdentifierScheme": "WEKO"}, {"nameIdentifier": "20401896", "nameIdentifierScheme": "e-Rad", "nameIdentifierURI": "https://kaken.nii.ac.jp/ja/search/?qm=20401896"}]}]}, "item_4_description_21": {"attribute_name": "抄録", "attribute_value_mlt": [{"subitem_description": "A 64-kb SRAM circuit with a single bit line (BL) for reading and with two BLs for writing was designed. Single-BL reading is achieved by using a left access transistor and a left shared reading port. We designed the cell layout and confirmed that there is no area penalty for producing two word lines in a memory cell. An analysis of butterfly plots clearly confirms that the single-BL SRAM has the larger static noise margin than the two-BL one. It is confirmed that the static noise margin in the single-BL SRAM is further increased when the BL is precharged to not VDD but to the lower value in the range of VDD/2 to 3VDD/4. In addition, a new sense amplifier circuit without reference voltage is proposed for single-BL reading. We also propose a divided word line architecture for writing to maintain the static noise margin for unwritten blocks. © 2011 IEEE.", "subitem_description_type": "Abstract"}]}, "item_4_identifier_registration": {"attribute_name": "ID登録", "attribute_value_mlt": [{"subitem_identifier_reg_text": "10.24517/00008406", "subitem_identifier_reg_type": "JaLC"}]}, "item_4_publisher_17": {"attribute_name": "出版者", "attribute_value_mlt": [{"subitem_publisher": "IEEE"}]}, "item_4_relation_12": {"attribute_name": "DOI", "attribute_value_mlt": [{"subitem_relation_type": "isIdenticalTo", "subitem_relation_type_id": {"subitem_relation_type_id_text": "10.1109/MWSCAS.2011.6026600", "subitem_relation_type_select": "DOI"}}]}, "item_4_rights_23": {"attribute_name": "権利", "attribute_value_mlt": [{"subitem_rights": "© 2011 IEEE"}]}, "item_4_source_id_9": {"attribute_name": "ISSN", "attribute_value_mlt": [{"subitem_source_identifier": "1548-3746", "subitem_source_identifier_type": "ISSN"}]}, "item_4_version_type_25": {"attribute_name": "著者版フラグ", "attribute_value_mlt": [{"subitem_version_resource": "http://purl.org/coar/version/c_970fb48d4fbd8a85", "subitem_version_type": "VoR"}]}, "item_creator": {"attribute_name": "著者", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "Nakata, Shunji"}], "nameIdentifiers": [{"nameIdentifier": "11794", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Suzuki, Hirotsugu"}], "nameIdentifiers": [{"nameIdentifier": "11795", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Makino, Hiroshi"}], "nameIdentifiers": [{"nameIdentifier": "11796", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Mutoh, Shin\u0027ichiro"}], "nameIdentifiers": [{"nameIdentifier": "11797", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Miyama, Masayuki"}], "nameIdentifiers": [{"nameIdentifier": "535", "nameIdentifierScheme": "WEKO"}, {"nameIdentifier": "30324106", "nameIdentifierScheme": "金沢大学研究者情報", "nameIdentifierURI": "http://ridb.kanazawa-u.ac.jp/public/detail.php?kaken=30324106"}, {"nameIdentifier": "30324106", "nameIdentifierScheme": "研究者番号", "nameIdentifierURI": "https://nrid.nii.ac.jp/nrid/1000030324106"}]}, {"creatorNames": [{"creatorName": "Matsuda, Yoshio"}], "nameIdentifiers": [{"nameIdentifier": "10707", "nameIdentifierScheme": "WEKO"}, {"nameIdentifier": "20401896", "nameIdentifierScheme": "金沢大学研究者情報", "nameIdentifierURI": "http://ridb.kanazawa-u.ac.jp/public/detail.php?kaken=20401896"}, {"nameIdentifier": "20401896", "nameIdentifierScheme": "研究者番号", "nameIdentifierURI": "https://nrid.nii.ac.jp/nrid/1000020401896"}]}]}, "item_files": {"attribute_name": "ファイル情報", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2017-10-03"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "TE-PR-MATSUDA-Y-6026600.pdf", "filesize": [{"value": "324.2 kB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_11", "mimetype": "application/pdf", "size": 324200.0, "url": {"label": "TE-PR-MATSUDA-Y-6026600.pdf", "url": "https://kanazawa-u.repo.nii.ac.jp/record/8419/files/TE-PR-MATSUDA-Y-6026600.pdf"}, "version_id": "e3223377-e114-4b06-a557-1cf74a6bfd2d"}]}, "item_language": {"attribute_name": "言語", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"resourcetype": "journal article", "resourceuri": "http://purl.org/coar/resource_type/c_6501"}]}, "item_title": "Increasing static noise margin of single-bit-line SRAM by lowering bit-line voltage during reading", "item_titles": {"attribute_name": "タイトル", "attribute_value_mlt": [{"subitem_title": "Increasing static noise margin of single-bit-line SRAM by lowering bit-line voltage during reading"}]}, "item_type_id": "4", "owner": "3", "path": ["4187"], "permalink_uri": "https://doi.org/10.24517/00008406", "pubdate": {"attribute_name": "公開日", "attribute_value": "2017-10-03"}, "publish_date": "2017-10-03", "publish_status": "0", "recid": "8419", "relation": {}, "relation_version_is_last": true, "title": ["Increasing static noise margin of single-bit-line SRAM by lowering bit-line voltage during reading"], "weko_shared_id": 3}
Increasing static noise margin of single-bit-line SRAM by lowering bit-line voltage during reading
https://doi.org/10.24517/00008406
https://doi.org/10.24517/00008406c7068ec0-8430-43c5-a641-089e5f1dcd55
名前 / ファイル | ライセンス | アクション |
---|---|---|
TE-PR-MATSUDA-Y-6026600.pdf (324.2 kB)
|
Item type | 学術雑誌論文 / Journal Article(1) | |||||
---|---|---|---|---|---|---|
公開日 | 2017-10-03 | |||||
タイトル | ||||||
タイトル | Increasing static noise margin of single-bit-line SRAM by lowering bit-line voltage during reading | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
ID登録 | ||||||
ID登録 | 10.24517/00008406 | |||||
ID登録タイプ | JaLC | |||||
著者 |
Nakata, Shunji
× Nakata, Shunji× Suzuki, Hirotsugu× Makino, Hiroshi× Mutoh, Shin'ichiro× Miyama, Masayuki× Matsuda, Yoshio |
|||||
著者別表示 |
深山, 正幸
× 深山, 正幸× 松田, 吉雄 |
|||||
書誌情報 |
Midwest Symposium on Circuits and Systems p. 6026600, 発行日 2011-01-01 |
|||||
ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 1548-3746 | |||||
DOI | ||||||
関連タイプ | isIdenticalTo | |||||
識別子タイプ | DOI | |||||
関連識別子 | 10.1109/MWSCAS.2011.6026600 | |||||
出版者 | ||||||
出版者 | IEEE | |||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | A 64-kb SRAM circuit with a single bit line (BL) for reading and with two BLs for writing was designed. Single-BL reading is achieved by using a left access transistor and a left shared reading port. We designed the cell layout and confirmed that there is no area penalty for producing two word lines in a memory cell. An analysis of butterfly plots clearly confirms that the single-BL SRAM has the larger static noise margin than the two-BL one. It is confirmed that the static noise margin in the single-BL SRAM is further increased when the BL is precharged to not VDD but to the lower value in the range of VDD/2 to 3VDD/4. In addition, a new sense amplifier circuit without reference voltage is proposed for single-BL reading. We also propose a divided word line architecture for writing to maintain the static noise margin for unwritten blocks. © 2011 IEEE. | |||||
権利 | ||||||
権利情報 | © 2011 IEEE | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 |