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A 158 MS/s JPEG 2000 Codec with a bit-plane and pass parallel embedded block coder for low delay image transmission
https://doi.org/10.24517/00009915
https://doi.org/10.24517/000099154c5b058a-5dcc-4b79-b48e-86a6a43f1897
名前 / ファイル | ライセンス | アクション |
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TE-PR-MIYAMA-M-2025.pdf (1.6 MB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2017-10-03 | |||||
タイトル | ||||||
タイトル | A 158 MS/s JPEG 2000 Codec with a bit-plane and pass parallel embedded block coder for low delay image transmission | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
ID登録 | ||||||
ID登録 | 10.24517/00009915 | |||||
ID登録タイプ | JaLC | |||||
著者 |
Miyama, Masayuki
× Miyama, Masayuki× Inoie, Yuusuke× Kasuga, Takafumi× Inada, Ryouichi× Nakao, Masashi× Matsuda, Yoshio |
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著者別表示 |
深山, 正幸
× 深山, 正幸× 松田, 吉雄 |
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提供者所属 | ||||||
内容記述タイプ | Other | |||||
内容記述 | 金沢大学理工研究域電子情報学系 | |||||
書誌情報 |
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 巻 E91-A, 号 8, p. 2025-2034, 発行日 2008-08-01 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 0916-8508 | |||||
NCID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA10826239 | |||||
DOI | ||||||
関連タイプ | isIdenticalTo | |||||
識別子タイプ | DOI | |||||
関連識別子 | 10.1093/ietfec/e91-a.8.2025 | |||||
出版者 | ||||||
出版者 | IEICE transactions on communications electronics information and systems = 電子情報通信学会 | |||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | This paper describes a 158 MS/s JPEG 2000 codec with an embedded block coder (EBC) based on bit-plane and pass-parallel architecture. The EBC contains bit-plane coders (BPCs) corresponding to each bit-plane in a code-block. The upper and the lower bit-plane coding overlap in time with a 1-stripe and 1-column gap. The bit-modeling passes in the bit-plane coding also overlap in time with the same gap. These methods increase throughput by 30 times in comparison with the conventional. In addition, the methods support not only vertically causal mode, but also regular mode, which enhances the image quality. Furthermore, speculative decoding is adopted to increase throughput. This codec LSI was designed using 0.18/Limprocess. The core area is 4.7 x 4.7 mm2 and the frequency is 160 MHz. A system including the codec enables image transmission of PC desktop with 8 ms delay. Copyright © 2008 The Institute of Electronics, Information and Communication Engineers. | |||||
権利 | ||||||
権利情報 | Copyright (c) 2010 The Institute of Electronics, Information and Communication Engineers | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 |