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A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation(Digital, <Special Section>Low-Power LSI and Low-Power IP)
https://doi.org/10.24517/00007568
https://doi.org/10.24517/000075685cfe3901-0b20-45be-a588-99e2afcb390c
名前 / ファイル | ライセンス | アクション |
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2-5.pdf (736.7 kB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2017-10-03 | |||||
タイトル | ||||||
タイトル | A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation(Digital, <Special Section>Low-Power LSI and Low-Power IP) | |||||
言語 | ||||||
言語 | jpn | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
ID登録 | ||||||
ID登録 | 10.24517/00007568 | |||||
ID登録タイプ | JaLC | |||||
著者 |
Miyakoshi, Junichi
× Miyakoshi, Junichi× Murachi, Yuichiro× Hamano, Koji× Matsuno, Tetsuro× Miyama, Masayuki× Yoshimoto, Masahiko |
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著者別表示 |
深山, 正幸
× 深山, 正幸× 吉本, 雅彦 |
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提供者所属 | ||||||
内容記述タイプ | Other | |||||
内容記述 | 大学院自然科学研究科情報システム | |||||
書誌情報 |
IEICE transactions on electronics 巻 E88-C, 号 4, p. 559-569, 発行日 2005-04-01 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 0916-8524 | |||||
NCID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA10826283 | |||||
権利 | ||||||
権利情報 | 電子情報通信学会の許諾を得て登録 | |||||
権利 | ||||||
権利情報 | copyright© 2005 IEICE 許諾番号07RB0167 | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
関連URI | ||||||
識別子タイプ | URI | |||||
関連識別子 | http://search.ieice.org/ |