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Computationally efficient implementation of sarse-tap FIR adaptive filters with tap-position control on intel IA-32 processors
http://hdl.handle.net/2297/18070
http://hdl.handle.net/2297/1807009dd425d-81c8-41ca-afa9-d1373ed5eeba
名前 / ファイル | ライセンス | アクション |
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TE-PR-NAKAYAMA-K-292.pdf (1.5 MB)
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Item type | 会議発表論文 / Conference Paper(1) | |||||
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公開日 | 2017-10-03 | |||||
タイトル | ||||||
タイトル | Computationally efficient implementation of sarse-tap FIR adaptive filters with tap-position control on intel IA-32 processors | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||
資源タイプ | conference paper | |||||
著者 |
Hirano, Akihiro
× Hirano, Akihiro× Nakayama, Kenji |
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提供者所属 | ||||||
内容記述タイプ | Other | |||||
内容記述 | 金沢大学理工研究域 電子情報学系 | |||||
書誌情報 |
International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) 2008, Bangkok, Thailand on February 8-11, 2009. p. 292-295, 発行日 2009-02-01 |
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出版者 | ||||||
出版者 | IEEE = Institute of Electrical and Electronics Engineers | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 |