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A sub-mW H.264 baseline-profile motion estimation processor core with a VLSI-oriented block partitioning strategy and SIMD/systolic-array architecture
https://doi.org/10.24517/00009971
https://doi.org/10.24517/00009971c80692a1-a588-44dd-835c-49cd2acee998
名前 / ファイル | ライセンス | アクション |
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TE-PR-MIYAMA-M-3623.pdf (1.9 MB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2017-10-03 | |||||
タイトル | ||||||
タイトル | A sub-mW H.264 baseline-profile motion estimation processor core with a VLSI-oriented block partitioning strategy and SIMD/systolic-array architecture | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
ID登録 | ||||||
ID登録 | 10.24517/00009971 | |||||
ID登録タイプ | JaLC | |||||
著者 |
Miyakoshi, Junichi
× Miyakoshi, Junichi× Murachi, Yuichiro× Matsuno, Tetsuro× Hamamoto, Masaki× Iinuma, Takahiro× Ishihara, Tomokazu× Kawaguchi, Hiroshi× Miyama, Masayuki× Yoshimoto, Masahiko |
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著者別表示 |
深山, 正幸
× 深山, 正幸× 吉本, 雅彦 |
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提供者所属 | ||||||
内容記述タイプ | Other | |||||
内容記述 | 金沢大学理工研究域電子情報学系 | |||||
書誌情報 |
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 巻 E89-A, 号 12, p. 3623-3633, 発行日 2006-12-01 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 0916-8508 | |||||
NCID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AN10467885 | |||||
DOI | ||||||
関連タイプ | isIdenticalTo | |||||
識別子タイプ | DOI | |||||
関連識別子 | 10.1093/ietfec/e89-a.12.3623 | |||||
出版者 | ||||||
出版者 | IEICE 電子情報通信学会 | |||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | We propose a sub-mW H.264 baseline-profile motion estimation processor for portable video applications. It features a VLSI-oriented block partitioning strategy and low-power SIMD/systolic-array datapath architecture, where the datapath can be switched between an SIMD and systolic array depending on processing flow. The processor supports all the seven kinds of block modes, and can handle three reference frames for a CIF (352 × 288) 30-fps to QCIF (176 × 144) 15-fps sequences with a quarter-pixel accuracy. It integrates 3.3 million transistors, and occupies 2.8×3.1 mm2 in a 130-nm CMOS technology. The proposed processor achieves a power of 800 μW in a QCIF 15-fps sequence with one reference picture. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers. | |||||
権利 | ||||||
権利情報 | (c) IEICE 電子情報通信学会 | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
関連URI | ||||||
識別子タイプ | URI | |||||
関連識別子 | http://www.ieice.org/jpn/index.html | |||||
関連URI | ||||||
識別子タイプ | URI | |||||
関連識別子 | http://ci.nii.ac.jp/naid/110007537867 |