Computer simulation, Demagnetization, Eddy currents, Electric fault location, Electric network topology, Electric surges, Magnetic cores, Magnetic flux, Permanent magnets, Short circuit currents, Waveform analysis, Magnetic current limiters, Power semiconductor devices, Limiters
International Journal of Applied Electromagnetics and Mechanics
巻
11
号
4
ページ
245 - 254
発行年
2000
ISSN
1383-5416
NCID
AA11051133
出版者
The Japan Society of Applied Electromagnetics and Mechanics (JSAEM) = 日本AEM学会
抄録
Different topological configurations for a passive magnetic current limiter consisting of a permanent magnet and saturable core are discussed in this paper. The models for a series/parallel biasing mode, and a single/three phase supply system have been fabricated and the experiments have been carried out for the performance evaluation. Using tableau method, the transient performance of different models has been simulated. The feasibility of applying the current limiter for the protection of power semiconductor devices in moderately low voltage applications is investigated.
Studies of Various Topologies of Passive Magnetic Current Limiter
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TE-PR-YAMADA-S-180.pdf
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