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A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation(Digital, <Special Section>Low-Power LSI and Low-Power IP) 深山, 正幸 吉本, 雅彦 Miyakoshi, Junichi 10129 Murachi, Yuichiro 10130 Hamano, Koji 10131 Matsuno, Tetsuro 10132 Miyama, Masayuki 535 30324106 30324106 Yoshimoto, Masahiko 9900 30324099 30324099 大学院自然科学研究科情報システム journal article 2005-04-01 VoR application/pdf IEICE transactions on electronics 4 E88-C 559 569 AA10826283 0916-8524 https://kanazawa-u.repo.nii.ac.jp/record/7581/files/2-5.pdf https://doi.org/10.24517/00007568 http://hdl.handle.net/2297/6978 https://kanazawa-u.repo.nii.ac.jp/records/7581 jpn http://search.ieice.org/ 電子情報通信学会の許諾を得て登録 copyright© 2005 IEICE　許諾番号07RB0167