| アイテムタイプ |
学術雑誌論文 / Journal Article_default(1) |
| 公開日 |
2017-11-16 |
| タイトル |
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タイトル |
A Passive Current Limiter for Power Semiconductor Protection |
| 言語 |
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言語 |
eng |
| 資源タイプ |
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資源タイプ識別子 |
http://purl.org/coar/resource_type/c_6501 |
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資源タイプ |
journal article |
| ID登録 |
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ID登録 |
10.24517/00048885 |
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ID登録タイプ |
JaLC |
| 著者 |
岩原, 正吉
山田, 外史
Iwahara, Masayoshi
Sotoshi, Yamada
F.P., Dawson
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| 抄録 |
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内容記述タイプ |
Abstract |
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内容記述 |
Static power converters are being used increasingly in power system applications. The power semiconductor switches within the converter systems must be rated to accommodate power system fault currents and system overvoltages. Significant cost reductions can be attained by reducing the magnitude of power system fault currents. In this paper we propose the use of a novel passive current limiter to accomplish this task. The limiter consists of two magnetic devices connected in series and in magnetic counter opposition to each other. Each magnetic device consists of three slices of NdFeB permanent magnet material sandwiched between the three end poles of two ferrite E cores. Experimental and finite element results are presented and are found to be in good agreement with each other. The need for 3D modeling in the future is demonstrated. The operating characteristics of the current limiter are experimentally verified using a scaled down version of a power system. |
| 書誌情報 |
Conference Record - IAS Annual Meeting (IEEE Industry Applications Society)
巻 3,
p. 1298-1301,
発行日 1996-10
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| 出版者 |
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出版者 |
IEEE |
| ISSN |
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収録物識別子タイプ |
ISSN |
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収録物識別子 |
0197-2618 |
| 権利 |
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|
権利情報 |
Copyright © IEEE |
| 著者版フラグ |
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出版タイプ |
VoR |
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出版タイプResource |
http://purl.org/coar/version/c_970fb48d4fbd8a85 |
TE-PR-YAMADA-S-101.pdf (304.9 kB)
