{"created":"2023-07-27T06:24:30.166151+00:00","id":7432,"links":{},"metadata":{"_buckets":{"deposit":"ce3a65dd-e23f-46c9-a04a-61be3a92b0fb"},"_deposit":{"created_by":3,"id":"7432","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"7432"},"status":"published"},"_oai":{"id":"oai:kanazawa-u.repo.nii.ac.jp:00007432","sets":["934:935:936"]},"author_link":["353","9839"],"item_8_biblio_info_8":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"1985-06-01","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"1486","bibliographicPageStart":"1483","bibliographic_titles":[{"bibliographic_title":"Proceedings - IEEE International Symposium on Circuits and Systems"}]}]},"item_8_description_21":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"A simplified digital tuned-circuit extractor is proposed. An A/D converter and multipliers are not required. An A/D converter and multipliers are not required. The tuning frequency is determined only by a master clock. The tank circuit output noise is sufficiently suppressed by newly introduced error canceller. Although sampling frequency for the tank circuit is relatively low, the phase of the output signal is effectively detected. A computer simulation shows that phase adjusting for data sampling clock is stable. The proposed timing extractor is easily realized on digital integrated circuits.","subitem_description_type":"Abstract"}]},"item_8_publisher_17":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IEEE(Institute of Electrical and Electronics Engineers)"}]},"item_8_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"0271-4310","subitem_source_identifier_type":"ISSN"}]},"item_8_version_type_25":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Nakayama, Kenji"}],"nameIdentifiers":[{},{},{}]},{"creatorNames":[{"creatorName":"Kuriki, Satoshi"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-10-03"}],"displaytype":"detail","filename":"TE-PR-NAKAYAMA-K-1483.pdf","filesize":[{"value":"468.7 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"TE-PR-NAKAYAMA-K-1483.pdf","url":"https://kanazawa-u.repo.nii.ac.jp/record/7432/files/TE-PR-NAKAYAMA-K-1483.pdf"},"version_id":"99189a5c-5b2d-474a-90db-1401aa1be5d7"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"conference paper","resourceuri":"http://purl.org/coar/resource_type/c_5794"}]},"item_title":"A multiplier-less digital timing extractor circuit with round-off error canceller","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"A multiplier-less digital timing extractor circuit with round-off error canceller"}]},"item_type_id":"8","owner":"3","path":["936"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-10-03"},"publish_date":"2017-10-03","publish_status":"0","recid":"7432","relation_version_is_last":true,"title":["A multiplier-less digital timing extractor circuit with round-off error canceller"],"weko_creator_id":"3","weko_shared_id":-1},"updated":"2023-07-28T02:23:36.731952+00:00"}