@article{oai:kanazawa-u.repo.nii.ac.jp:00007466,
 author = {Morita, Yasuhiro and Fujiwara, Hidehiro and Noguchi, Hiroki and Kawakami, Kentaro and Miyakoshi, Junichi and Mikami, Shinji and Nii, Koji and Kawaguchi, Hiroshi and Yoshimoto, Masahiko},
 issue = {12},
 journal = {IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences},
 month = {Dec},
 note = {We propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the memory cells and wordline drivers, bitline voltage, and body bias voltage of load pMOSFETs are controlled according to read and write operations, which secures operation margins even at a low operation voltage. A self-aligned timing control with a dummy wordline and its feedback is also introduced to guarantee stable operation in a wide range of the supply voltage. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that a power reduction of 30 can be achieved at 100 MHz. In a 65-nm 64-Mb SRAM, a 74 power saving is expected at 1/6 of the maximum operating frequency. The performance penalty by the proposed scheme is less than 1, and area overhead is 5.6. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers., 元・大学院自然科学研究科, 現・神戸大学大学院自然科学研究科},
 pages = {3634--3641},
 title = {A 0.3-V operating, Vth-variation-tolerant SRAM under DVS environment for memory-rich SoC in 90-nm technology era and beyond},
 volume = {E89-A},
 year = {2006}
}