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Design techniques for switched capacitor adaptive line equlizer
http://hdl.handle.net/2297/3948
http://hdl.handle.net/2297/394890f57a87-60f2-4672-ab72-56e83dfce23f
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
TE-PR-NAKAYAMA-K-759.pdf (611.6 kB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||
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| 公開日 | 2017-10-03 | |||||
| タイトル | ||||||
| タイトル | Design techniques for switched capacitor adaptive line equlizer | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | journal article | |||||
| 著者 |
Nakayama, Kenji
× Nakayama, Kenji× Sato, Yayoi× Kuraishi, Yoshiaki |
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| 提供者所属 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | 金沢大学大学院自然科学研究科情報システム | |||||
| 提供者所属 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | 金沢大学工学部 | |||||
| 書誌情報 |
IEEE transactions on circuits and systems 巻 CAS-32, 号 8, p. 759-766, 発行日 1985-08-01 |
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| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 0098-4094 | |||||
| DOI | ||||||
| 関連タイプ | isIdenticalTo | |||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | https://doi.org/10.1109/tcs.1985.1085792 | |||||
| 出版者 | ||||||
| 出版者 | Institute of Electrical and Electronics Engineers (IEEE) | |||||
| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | Design techniques are described for a switched capacitor adaptive line equalizer which is applied to high-speed (200 kb/s) digital transmission over analog subscriber loops. An equalizer transfer function is approximated so as to minimize intersymbol interference of an isolated pulse response. Optimum pole-zero location, which is suited to line characteristics in a wide frequency band, is also discussed. In order to attain high accuracy capacitor ratios using a small unit capacitor, capacitor values are rounded off into equivalent integer values, and are discretely optimized using pole-zero deviation as an error criterion. The equalizer has a finite number of frequency responses which correspond to line lengths. Gain and delay time differences between the adjoining step responses are compressed. The switched capacitor line equalizer was fabricated using 3- mu m CMOS technology. Measured data were very close to designed performances. | |||||
| 著者版フラグ | ||||||
| 出版タイプ | VoR | |||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
