{"created":"2023-07-27T06:24:33.532969+00:00","id":7512,"links":{},"metadata":{"_buckets":{"deposit":"9608e1b8-3026-4561-8649-f218e5d2ed69"},"_deposit":{"created_by":3,"id":"7512","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"7512"},"status":"published"},"_oai":{"id":"oai:kanazawa-u.repo.nii.ac.jp:00007512","sets":["934:935:936"]},"author_link":["353","9984","9983"],"item_4_biblio_info_8":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"1985-08-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"8","bibliographicPageEnd":"766","bibliographicPageStart":"759","bibliographicVolumeNumber":"CAS-32","bibliographic_titles":[{"bibliographic_title":"IEEE transactions on circuits and systems"}]}]},"item_4_description_21":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Design techniques are described for a switched capacitor adaptive line equalizer which is applied to high-speed (200 kb/s) digital transmission over analog subscriber loops. An equalizer transfer function is approximated so as to minimize intersymbol interference of an isolated pulse response. Optimum pole-zero location, which is suited to line characteristics in a wide frequency band, is also discussed. In order to attain high accuracy capacitor ratios using a small unit capacitor, capacitor values are rounded off into equivalent integer values, and are discretely optimized using pole-zero deviation as an error criterion. The equalizer has a finite number of frequency responses which correspond to line lengths. Gain and delay time differences between the adjoining step responses are compressed. The switched capacitor line equalizer was fabricated using 3- mu m CMOS technology. Measured data were very close to designed performances.","subitem_description_type":"Abstract"}]},"item_4_description_5":{"attribute_name":"提供者所属","attribute_value_mlt":[{"subitem_description":"金沢大学大学院自然科学研究科情報システム","subitem_description_type":"Other"},{"subitem_description":"金沢大学工学部","subitem_description_type":"Other"}]},"item_4_publisher_17":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"Institute of Electrical and Electronics Engineers (IEEE)"}]},"item_4_relation_12":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isIdenticalTo","subitem_relation_type_id":{"subitem_relation_type_id_text":"https://doi.org/10.1109/tcs.1985.1085792","subitem_relation_type_select":"DOI"}}]},"item_4_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"0098-4094","subitem_source_identifier_type":"ISSN"}]},"item_4_version_type_25":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Nakayama, Kenji"}],"nameIdentifiers":[{"nameIdentifier":"353","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"00207945","nameIdentifierScheme":"e-Rad","nameIdentifierURI":"https://kaken.nii.ac.jp/ja/search/?qm=00207945"},{"nameIdentifier":"00207945","nameIdentifierScheme":"研究者番号","nameIdentifierURI":"https://nrid.nii.ac.jp/nrid/1000000207945"}]},{"creatorNames":[{"creatorName":"Sato, Yayoi"}],"nameIdentifiers":[{"nameIdentifier":"9983","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Kuraishi, Yoshiaki"}],"nameIdentifiers":[{"nameIdentifier":"9984","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-10-03"}],"displaytype":"detail","filename":"TE-PR-NAKAYAMA-K-759.pdf","filesize":[{"value":"611.6 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"TE-PR-NAKAYAMA-K-759.pdf","url":"https://kanazawa-u.repo.nii.ac.jp/record/7512/files/TE-PR-NAKAYAMA-K-759.pdf"},"version_id":"3705b74e-4d24-4c79-8c7b-2743ebdcf54c"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Design techniques for switched capacitor adaptive line equlizer","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Design techniques for switched capacitor adaptive line equlizer"}]},"item_type_id":"4","owner":"3","path":["936"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-10-03"},"publish_date":"2017-10-03","publish_status":"0","recid":"7512","relation_version_is_last":true,"title":["Design techniques for switched capacitor adaptive line equlizer"],"weko_creator_id":"3","weko_shared_id":3},"updated":"2024-06-20T06:13:37.769265+00:00"}