{"created":"2023-07-27T06:25:02.416799+00:00","id":8174,"links":{},"metadata":{"_buckets":{"deposit":"08e13f7b-ac19-4c1d-bb3b-54c536ba7ab7"},"_deposit":{"created_by":3,"id":"8174","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"8174"},"status":"published"},"_oai":{"id":"oai:kanazawa-u.repo.nii.ac.jp:00008174","sets":["4163:4171:4187"]},"author_link":["535","2278","10707","2717","11322"],"item_4_biblio_info_8":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2010-12-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"12","bibliographicPageEnd":"3293","bibliographicPageStart":"3284","bibliographicVolumeNumber":"E93-D","bibliographic_titles":[{"bibliographic_title":"IEICE Transactions on Information and Systems"}]}]},"item_4_creator_33":{"attribute_name":"著者別表示","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"深山, 正幸 "}],"nameIdentifiers":[{},{}]},{"creatorNames":[{"creatorName":"松田, 吉雄 "}],"nameIdentifiers":[{},{}]}]},"item_4_description_21":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"This paper describes an affine motion estimation processor for real-time video segmentation. The processor estimates the dominant motion of a target region with affine parameters. The processor is based on the Pseudo-M-estimator algorithm. Introduction of an image division method and a binary weight method to the original algorithm reduces data traffic and hardware costs. A pixel sampling method is proposed that reduces the clock frequency by 50%. The pixel pipeline architecture and a frame overlap method double throughput. The processor was prototyped on an FPGA; its function and performance were subsequently verified. It was also implemented as an ASIC. The core size is 5.0 × 5.0 mm2 in 0.18 μm process, standard cell technology. The ASIC can accommodate a VGA 30 fps video with 120 MHz clock frequency. Copyright© 2010.","subitem_description_type":"Abstract"}]},"item_4_description_5":{"attribute_name":"提供者所属","attribute_value_mlt":[{"subitem_description":"金沢大学理工研究域電子情報学系","subitem_description_type":"Other"}]},"item_4_identifier_registration":{"attribute_name":"ID登録","attribute_value_mlt":[{"subitem_identifier_reg_text":"10.24517/00008161","subitem_identifier_reg_type":"JaLC"}]},"item_4_publisher_17":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IEICE transactions on communications electronics information and systems = 電子情報通信学会"}]},"item_4_relation_12":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isIdenticalTo","subitem_relation_type_id":{"subitem_relation_type_id_text":"10.1587/transinf.E93.D.3284","subitem_relation_type_select":"DOI"}}]},"item_4_relation_28":{"attribute_name":"関連URI","attribute_value_mlt":[{"subitem_relation_type_id":{"subitem_relation_type_id_text":"http://www.jstage.jst.go.jp/article/transinf/E93.D/12/E93.D_3284/_article","subitem_relation_type_select":"URI"}}]},"item_4_rights_23":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"Copyright (c) 2010 The Institute of Electronics, Information and Communication Engineers"}]},"item_4_source_id_11":{"attribute_name":"NCID","attribute_value_mlt":[{"subitem_source_identifier":"AA10826272","subitem_source_identifier_type":"NCID"}]},"item_4_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"0916-8532","subitem_source_identifier_type":"ISSN"}]},"item_4_version_type_25":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yunbe, Yoshiki"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Miyama, Masayuki"}],"nameIdentifiers":[{},{},{}]},{"creatorNames":[{"creatorName":"Matsuda, Yoshio"}],"nameIdentifiers":[{},{},{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-10-03"}],"displaytype":"detail","filename":"TE-PR-MIYAMA-M-3284.pdf","filesize":[{"value":"2.2 MB"}],"format":"application/pdf","licensetype":"license_11","mimetype":"application/pdf","url":{"label":"TE-PR-MIYAMA-M-3284.pdf","url":"https://kanazawa-u.repo.nii.ac.jp/record/8174/files/TE-PR-MIYAMA-M-3284.pdf"},"version_id":"bc134913-04e4-4aee-87dd-8b443ba67e21"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"A VGA 30fps affine motion model estimation VLSI for real-time video segmentation","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"A VGA 30fps affine motion model estimation VLSI for real-time video segmentation"}]},"item_type_id":"4","owner":"3","path":["4187"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-10-03"},"publish_date":"2017-10-03","publish_status":"0","recid":"8174","relation_version_is_last":true,"title":["A VGA 30fps affine motion model estimation VLSI for real-time video segmentation"],"weko_creator_id":"3","weko_shared_id":3},"updated":"2023-07-27T10:34:43.672932+00:00"}