{"created":"2023-07-27T06:25:07.086825+00:00","id":8285,"links":{},"metadata":{"_buckets":{"deposit":"c6809f23-22a8-4d05-b33d-b478e36c3a9d"},"_deposit":{"created_by":3,"id":"8285","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"8285"},"status":"published"},"_oai":{"id":"oai:kanazawa-u.repo.nii.ac.jp:00008285","sets":["934:935:936"]},"author_link":["353","377"],"item_8_biblio_info_8":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2008-01-01","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"295","bibliographicPageStart":"292","bibliographic_titles":[{"bibliographic_title":"The International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2008)"}]}]},"item_8_description_21":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"This paper presents an computationally ef cient implementation of sparse-tap FIR adaptive lters with tapposition control on Intel IA-32 processors with single-instruction multiple-data (SIMD) capability. In order to overcome randomorder memory access which prevents a ectorization, a blockbased processing and a re-ordering buffer are introduced. A dynamic register allocation and the use of memory-to-register operations help the maximization of the loop-unrolling level. Up to 66percent speedup is achieved.","subitem_description_type":"Abstract"}]},"item_8_description_22":{"attribute_name":"内容記述","attribute_value_mlt":[{"subitem_description":"Organized by the Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technology Association (ECTI) Co-organized by GCEO-NGIT, Hokkaido University Technical sponsored by IEEE Circuits and Systems Society In cooperation with the Institute of Electronics, Information and Communication Engineering (IEICE)","subitem_description_type":"Other"}]},"item_8_description_5":{"attribute_name":"提供者所属","attribute_value_mlt":[{"subitem_description":"金沢大学理工研究域　電子情報学系","subitem_description_type":"Other"}]},"item_8_publisher_17":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IEEE = Institute of Electrical and Electronics Engineers"}]},"item_8_version_type_25":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hirano, Akihiro"},{"creatorName":"ヒラノ, アキヒロ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{},{},{}]},{"creatorNames":[{"creatorName":"Nakayama, Kenji"}],"nameIdentifiers":[{},{},{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-10-03"}],"displaytype":"detail","filename":"TE-PR-HIRANO-A-292.pdf","filesize":[{"value":"109.9 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"TE-PR-HIRANO-A-292.pdf","url":"https://kanazawa-u.repo.nii.ac.jp/record/8285/files/TE-PR-HIRANO-A-292.pdf"},"version_id":"64e17988-0370-44f8-a802-1756aee96ff6"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"conference paper","resourceuri":"http://purl.org/coar/resource_type/c_5794"}]},"item_title":"Computationally efficient implementation of sarse-tap FIR adaptive filters with tap-position control on intel IA-32 processors","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Computationally efficient implementation of sarse-tap FIR adaptive filters with tap-position control on intel IA-32 processors"}]},"item_type_id":"8","owner":"3","path":["936"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-10-03"},"publish_date":"2017-10-03","publish_status":"0","recid":"8285","relation_version_is_last":true,"title":["Computationally efficient implementation of sarse-tap FIR adaptive filters with tap-position control on intel IA-32 processors"],"weko_creator_id":"3","weko_shared_id":-1},"updated":"2023-07-28T02:11:10.996117+00:00"}