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Increasing static noise margin of single-bit-line SRAM by lowering bit-line voltage during reading
https://doi.org/10.24517/00008406
https://doi.org/10.24517/00008406c7068ec0-8430-43c5-a641-089e5f1dcd55
| 名前 / ファイル | ライセンス | アクション |
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TE-PR-MATSUDA-Y-6026600.pdf (324.2 kB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||||||
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| 公開日 | 2017-10-03 | |||||||||
| タイトル | ||||||||||
| タイトル | Increasing static noise margin of single-bit-line SRAM by lowering bit-line voltage during reading | |||||||||
| 言語 | ||||||||||
| 言語 | eng | |||||||||
| 資源タイプ | ||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||||
| 資源タイプ | journal article | |||||||||
| ID登録 | ||||||||||
| ID登録 | 10.24517/00008406 | |||||||||
| ID登録タイプ | JaLC | |||||||||
| 著者 |
Nakata, Shunji
× Nakata, Shunji× Suzuki, Hirotsugu× Makino, Hiroshi× Mutoh, Shin'ichiro× Miyama, Masayuki× Matsuda, Yoshio |
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| 著者別表示 |
深山, 正幸
× 深山, 正幸
× 松田, 吉雄
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| 書誌情報 |
Midwest Symposium on Circuits and Systems p. 6026600, 発行日 2011-01-01 |
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| ISSN | ||||||||||
| 収録物識別子タイプ | ISSN | |||||||||
| 収録物識別子 | 1548-3746 | |||||||||
| DOI | ||||||||||
| 関連タイプ | isIdenticalTo | |||||||||
| 識別子タイプ | DOI | |||||||||
| 関連識別子 | 10.1109/MWSCAS.2011.6026600 | |||||||||
| 出版者 | ||||||||||
| 出版者 | IEEE | |||||||||
| 抄録 | ||||||||||
| 内容記述タイプ | Abstract | |||||||||
| 内容記述 | A 64-kb SRAM circuit with a single bit line (BL) for reading and with two BLs for writing was designed. Single-BL reading is achieved by using a left access transistor and a left shared reading port. We designed the cell layout and confirmed that there is no area penalty for producing two word lines in a memory cell. An analysis of butterfly plots clearly confirms that the single-BL SRAM has the larger static noise margin than the two-BL one. It is confirmed that the static noise margin in the single-BL SRAM is further increased when the BL is precharged to not VDD but to the lower value in the range of VDD/2 to 3VDD/4. In addition, a new sense amplifier circuit without reference voltage is proposed for single-BL reading. We also propose a divided word line architecture for writing to maintain the static noise margin for unwritten blocks. © 2011 IEEE. | |||||||||
| 権利 | ||||||||||
| 権利情報 | © 2011 IEEE | |||||||||
| 著者版フラグ | ||||||||||
| 出版タイプ | VoR | |||||||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||||||
