@article{oai:kanazawa-u.repo.nii.ac.jp:00008419,
 author = {深山, 正幸 and 松田, 吉雄 and Nakata, Shunji and Suzuki, Hirotsugu and Makino, Hiroshi and Mutoh, Shin'ichiro and Miyama, Masayuki and Matsuda, Yoshio},
 journal = {Midwest Symposium on Circuits and Systems},
 month = {Jan},
 note = {A 64-kb SRAM circuit with a single bit line (BL) for reading and with two BLs for writing was designed. Single-BL reading is achieved by using a left access transistor and a left shared reading port. We designed the cell layout and confirmed that there is no area penalty for producing two word lines in a memory cell. An analysis of butterfly plots clearly confirms that the single-BL SRAM has the larger static noise margin than the two-BL one. It is confirmed that the static noise margin in the single-BL SRAM is further increased when the BL is precharged to not VDD but to the lower value in the range of VDD/2 to 3VDD/4. In addition, a new sense amplifier circuit without reference voltage is proposed for single-BL reading. We also propose a divided word line architecture for writing to maintain the static noise margin for unwritten blocks. © 2011 IEEE.},
 title = {Increasing static noise margin of single-bit-line SRAM by lowering bit-line voltage during reading},
 year = {2011}
}