{"created":"2023-07-27T06:25:37.478065+00:00","id":8996,"links":{},"metadata":{"_buckets":{"deposit":"804c11a3-bf6c-4e99-99ae-e8751ad0cd68"},"_deposit":{"created_by":3,"id":"8996","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"8996"},"status":"published"},"_oai":{"id":"oai:kanazawa-u.repo.nii.ac.jp:00008996","sets":["934:935:936"]},"author_link":["353","377"],"item_4_biblio_info_8":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2012-01-01","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"245","bibliographicPageStart":"241","bibliographic_titles":[{"bibliographic_title":"第27回信号処理シンポジウム講演論文集 = Proc. of 27th SIP Symposium"}]}]},"item_4_description_21":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"This paper presents efficient implementa- tion of RLS-based adaptive filters with a large number of taps on nVIDIA GeForce graphics processing unit (GPU) and CUDA software development environment. Modification of the order and the combination of calcu- lations reduces the number of accesses to slow off-chip memory. Assigning tasks into multiple threads also takes memory access order into account. Multiple shader pro- cessor arrays are used to handle a large matrix. For a 8192-tap case, a GPU program is almost 30-times faster than a CPU program. Real-time processing is possible for an 8kHz-sampling and 512-tap case by us- ing 32 shader processors, which is only 25% of GeForce 8800GTS.","subitem_description_type":"Abstract"}]},"item_4_publisher_17":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"電子情報通信学会 = The Institute of Electronics, Information and Communication Engineers"}]},"item_4_relation_28":{"attribute_name":"関連URI","attribute_value_mlt":[{"subitem_relation_type_id":{"subitem_relation_type_id_text":"http://www.ieice.org/jpn/index.html","subitem_relation_type_select":"URI"}}]},"item_4_rights_23":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"(c) 2012 電子情報通信学会"}]},"item_4_version_type_25":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hirano, Akihiro"}],"nameIdentifiers":[{},{},{}]},{"creatorNames":[{"creatorName":"Nakayama, Kenji"}],"nameIdentifiers":[{},{},{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-10-03"}],"displaytype":"detail","filename":"TE-PR-HIRANO-A-241.pdf","filesize":[{"value":"104.2 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"TE-PR-HIRANO-A-241.pdf","url":"https://kanazawa-u.repo.nii.ac.jp/record/8996/files/TE-PR-HIRANO-A-241.pdf"},"version_id":"1d159372-0257-4c3f-934c-cf0d38d0f41b"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Efficient Implementation of RLS-Based Adaptive Filterson nVIDIA GeForce Graphics Processing Unit","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Efficient Implementation of RLS-Based Adaptive Filterson nVIDIA GeForce Graphics Processing Unit"}]},"item_type_id":"4","owner":"3","path":["936"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-10-03"},"publish_date":"2017-10-03","publish_status":"0","recid":"8996","relation_version_is_last":true,"title":["Efficient Implementation of RLS-Based Adaptive Filterson nVIDIA GeForce Graphics Processing Unit"],"weko_creator_id":"3","weko_shared_id":3},"updated":"2023-07-27T09:48:44.034238+00:00"}