{"created":"2023-07-27T06:25:50.127688+00:00","id":9296,"links":{},"metadata":{"_buckets":{"deposit":"e3bdf235-33fa-4bd7-afe4-68f90257b0cd"},"_deposit":{"created_by":3,"id":"9296","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"9296"},"status":"published"},"_oai":{"id":"oai:kanazawa-u.repo.nii.ac.jp:00009296","sets":["934:935:936"]},"author_link":["13335","13334","10707","13337","13336","13338"],"item_4_biblio_info_8":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2016-05-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"5","bibliographicPageEnd":"928","bibliographicPageStart":"917","bibliographicVolumeNumber":"E99.A","bibliographic_titles":[{"bibliographic_title":"IEICE transactions on fundamentals of electronics, communications and computer sciences"}]}]},"item_4_description_21":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"A Field Programmable Sequencer and Memory (FPSM), which is a programmable unit exclusively optimized for peripherals on a micro controller unit, is proposed. The FPSM functions as not only the peripherals but also the standard built-in memory. The FPSM provides easier programmability with a smaller area overhead, especially when compared with the FPGA. The FPSM is implemented on the FPGA and the programmability and performance for basic peripherals such as the 8 bit counter and 8 bit accuracy Pulse Width Modulation are emulated on the FPGA. Furthermore, the FPSM core with a 4K bit SRAM is fabricated in 0.18µm 5 metal CMOS process technology. The FPSM is an half the area of FPGA, its power consumption is less than one-fifth.","subitem_description_type":"Abstract"}]},"item_4_description_22":{"attribute_name":"内容記述","attribute_value_mlt":[{"subitem_description":"Embargo Period 6 months","subitem_description_type":"Other"}]},"item_4_publisher_17":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IEICE 電子情報通信学会"}]},"item_4_relation_12":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isIdenticalTo","subitem_relation_type_id":{"subitem_relation_type_id_text":"10.1587/transfun.E99.A.917","subitem_relation_type_select":"DOI"}}]},"item_4_relation_28":{"attribute_name":"関連URI","attribute_value_mlt":[{"subitem_relation_type_id":{"subitem_relation_type_id_text":"https://www.jstage.jst.go.jp/browse/transfun","subitem_relation_type_select":"URI"}},{"subitem_relation_type_id":{"subitem_relation_type_id_text":"http://www.ieice.org/jpn/","subitem_relation_type_select":"URI"}}]},"item_4_rights_23":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"Copyright © 2016 The Institute of Electronics, Information and Communication Engineers"}]},"item_4_source_id_11":{"attribute_name":"NCID","attribute_value_mlt":[{"subitem_source_identifier":"AA10826239","subitem_source_identifier_type":"NCID"}]},"item_4_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"0916-8508","subitem_source_identifier_type":"ISSN"}]},"item_4_version_type_25":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kawamura, Yoshifumi"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Okada, Naoya"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Matsuda, Yoshio"}],"nameIdentifiers":[{},{},{}]},{"creatorNames":[{"creatorName":"Matsumura, Tetsuya"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Makino, Hiroshi"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Arimoto, Kazutami"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-10-03"}],"displaytype":"detail","filename":"TE-PR-MATSUDA-Y-917-final.pdf","filesize":[{"value":"955.7 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"TE-PR-MATSUDA-Y-917-final.pdf","url":"https://kanazawa-u.repo.nii.ac.jp/record/9296/files/TE-PR-MATSUDA-Y-917-final.pdf"},"version_id":"96f20545-c9bb-4ffe-872e-01d5fddfb1c7"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals"}]},"item_type_id":"4","owner":"3","path":["936"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-10-03"},"publish_date":"2017-10-03","publish_status":"0","recid":"9296","relation_version_is_last":true,"title":["A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals"],"weko_creator_id":"3","weko_shared_id":-1},"updated":"2023-07-28T01:56:34.731509+00:00"}