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A new realization of sum of products and transposed sum of products implementation by partitioned arithmetic
http://hdl.handle.net/2297/18278
http://hdl.handle.net/2297/182784e6a40ca-c53d-4bed-b0f3-64130384eb64
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
TE-PR-NAKAYAMA-K-404.pdf (331.8 kB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2017-10-03 | |||||
| タイトル | ||||||
| タイトル | A new realization of sum of products and transposed sum of products implementation by partitioned arithmetic | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | journal article | |||||
| 著者 |
Nakayama, Kenji
× Nakayama, Kenji |
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| 提供者所属 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | 金沢大学理工研究域 電子情報学系 | |||||
| 書誌情報 |
IEEE transactions on circuits and systems 巻 29, 号 6, p. 404-408, 発行日 1982-06-01 |
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| DOI | ||||||
| 関連タイプ | isIdenticalTo | |||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | https://doi.org/10.1109/tcs.1982.1085161 | |||||
| 出版者 | ||||||
| 出版者 | IEEE = Institute of Electrical and Electronics Engineers | |||||
| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | A new approach to the implmentation of sum of products (SP) and transposed sum of products (TSP) using partitioned arithmetic is proposed. This aproach makes it possible to realize SP and TSP with recent advanced semiconductor memory technology without multipliers. It is also shown to offer signficant reductions in memory capacity requirement and computational complexity. Dynamic range constraints and output roundoff noise analysis are also discussed. | |||||
| 著者版フラグ | ||||||
| 出版タイプ | VoR | |||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
