@article{oai:kanazawa-u.repo.nii.ac.jp:00009928,
 author = {深山, 正幸 and 松田, 吉雄 and Miyama, Masayuki and Inoie, Yuusuke and Kasuga, Takafumi and Inada, Ryouichi and Nakao, Masashi and Matsuda, Yoshio},
 issue = {8},
 journal = {IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences},
 month = {Aug},
 note = {This paper describes a 158 MS/s JPEG 2000 codec with an embedded block coder (EBC) based on bit-plane and pass-parallel architecture. The EBC contains bit-plane coders (BPCs) corresponding to each bit-plane in a code-block. The upper and the lower bit-plane coding overlap in time with a 1-stripe and 1-column gap. The bit-modeling passes in the bit-plane coding also overlap in time with the same gap. These methods increase throughput by 30 times in comparison with the conventional. In addition, the methods support not only vertically causal mode, but also regular mode, which enhances the image quality. Furthermore, speculative decoding is adopted to increase throughput. This codec LSI was designed using 0.18/Limprocess. The core area is 4.7 x 4.7 mm2 and the frequency is 160 MHz. A system including the codec enables image transmission of PC desktop with 8 ms delay. Copyright © 2008 The Institute of Electronics, Information and Communication Engineers., 金沢大学理工研究域電子情報学系},
 pages = {2025--2034},
 title = {A 158 MS/s JPEG 2000 Codec with a bit-plane and pass parallel embedded block coder for low delay image transmission},
 volume = {E91-A},
 year = {2008}
}