@article{oai:kanazawa-u.repo.nii.ac.jp:00009984,
 author = {深山, 正幸 and 吉本, 雅彦 and Miyakoshi, Junichi and Murachi, Yuichiro and Matsuno, Tetsuro and Hamamoto, Masaki and Iinuma, Takahiro and Ishihara, Tomokazu and Kawaguchi, Hiroshi and Miyama, Masayuki and Yoshimoto, Masahiko},
 issue = {12},
 journal = {IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences},
 month = {Dec},
 note = {We propose a sub-mW H.264 baseline-profile motion estimation processor for portable video applications. It features a VLSI-oriented block partitioning strategy and low-power SIMD/systolic-array datapath architecture, where the datapath can be switched between an SIMD and systolic array depending on processing flow. The processor supports all the seven kinds of block modes, and can handle three reference frames for a CIF (352 × 288) 30-fps to QCIF (176 × 144) 15-fps sequences with a quarter-pixel accuracy. It integrates 3.3 million transistors, and occupies 2.8×3.1 mm2 in a 130-nm CMOS technology. The proposed processor achieves a power of 800 μW in a QCIF 15-fps sequence with one reference picture. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers., 金沢大学理工研究域電子情報学系},
 pages = {3623--3633},
 title = {A sub-mW H.264 baseline-profile motion estimation processor core with a VLSI-oriented block partitioning strategy and SIMD/systolic-array architecture},
 volume = {E89-A},
 year = {2006}
}