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階層形神経回路網のデイジタル構成におけるビット数低減方法
http://hdl.handle.net/2297/18377
http://hdl.handle.net/2297/18377272972b7-a2ce-45bd-b38c-c7669434a14f
名前 / ファイル | ライセンス | アクション |
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TE-PR-NAKAYAMA-K-1336.pdf (837.7 kB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2017-10-03 | |||||
タイトル | ||||||
タイトル | 階層形神経回路網のデイジタル構成におけるビット数低減方法 | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | Reduction in Number of Bits for Digital Realization of Multilayer Neural Networks | |||||
言語 | ||||||
言語 | jpn | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
著者 |
中山, 謙二
× 中山, 謙二× 猪股, 悟× 竹内, 由幸 |
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提供者所属 | ||||||
内容記述タイプ | Other | |||||
内容記述 | 金沢大学理工研究域 電子情報学系 | |||||
書誌情報 |
電子情報通信学会論文誌. D-II, 情報・システム, II-パターン処理 = IEICE The transactions of the Institute of Electronics, Information and Communicat 巻 J73-D-II, 号 8, p. 1336-1345, 発行日 1990-08-01 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 0915-1923 | |||||
NCID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AA11340957 | |||||
出版者 | ||||||
出版者 | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences = 電子情報通信学会 | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 |