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Vision Chip Architecture for Detecting Line of Sight Including Saccade
https://doi.org/10.24517/00007699
https://doi.org/10.24517/00007699cd0d0e12-83c1-4c3c-93a2-2c7f843bcb62
| 名前 / ファイル | ライセンス | アクション |
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TE-PR-AKITA-J-11-1605.pdf (3.3 MB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||||||
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| 公開日 | 2017-10-03 | |||||||||
| タイトル | ||||||||||
| タイトル | Vision Chip Architecture for Detecting Line of Sight Including Saccade | |||||||||
| 言語 | ||||||||||
| 言語 | jpn | |||||||||
| 資源タイプ | ||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||||
| 資源タイプ | journal article | |||||||||
| ID登録 | ||||||||||
| ID登録 | 10.24517/00007699 | |||||||||
| ID登録タイプ | JaLC | |||||||||
| 著者 |
Akita, Junichi
× Akita, Junichi× Takagi, Hiroaki× Nagasaki, Takeshi× Toda, Masashi× Kawashima, Toshio× Kitagawa, Akio |
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| 著者別表示 |
秋田, 純一
× 秋田, 純一
× 北川, 章夫
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| 提供者所属 | ||||||||||
| 内容記述タイプ | Other | |||||||||
| 内容記述 | 金沢大学融合研究域融合科学系 / 金沢大学大学院自然科学研究科情報システム | |||||||||
| 書誌情報 |
IEICE transactions on electronics 巻 E89-C, 号 11, p. 1605-1611, 発行日 2006-11-01 |
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| ISSN | ||||||||||
| 収録物識別子タイプ | ISSN | |||||||||
| 収録物識別子 | 0916-8524 | |||||||||
| NCID | ||||||||||
| 収録物識別子タイプ | NCID | |||||||||
| 収録物識別子 | AA10826283 | |||||||||
| 抄録 | ||||||||||
| 内容記述タイプ | Abstract | |||||||||
| 内容記述 | Rapid eye motion, or so called saccade, is a very quick eye motion which always occurs regardless of our intention. Although the line of sight (LOS) with saccade tracking is expected to be used for a new type of computer-human interface, it is impossible to track it using the conventional video camera, because of its speed which is often up to 600 degrees per second. Vision Chip is an intelligent image sensor which has the photo receptor and the image processing circuitry on a single chip, which can process the acquired image information by keeping its spatial parallelism. It has also the ability of implementing the very compact integrated vision system. In this paper, we describe the vision chip architecture which has the capability of detecting the line of sight from infrared eye image, with the processing speed supporting the saccade tracking. The vision chip described here has the pixel parallel processing architecture, with the node automata for each pixel as image processing. The acquired image is digitized to two flags indicating the Purkinje's image and the pupil by comparators at first. The digitized images are then shrunk, followed by several steps of expanding by node automata located at each pixel. The shrinking process is kept executed until all the pixels disappear, and the pixel disappearing at last indicates the center of the Purkinje's image and the pupil. This disappearing step is detected by the projection circuitry in pixel circuit for fast operation, and the coordinates of the center of the Purkinje's image and the pupil are generated by the simple encoders. We describe the whole architecture of this vision chip, as well as the pixel architecture. We also describe the evaluation of proposed algorithm with numerical simulation, as well as processing speed using FPGA, and improvement in resolution using column parallel architecture. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers. | |||||||||
| 権利 | ||||||||||
| 権利情報 | 電子情報通信学会の許諾を得て登録 | |||||||||
| 権利 | ||||||||||
| 権利情報 | copyright© 2006 IEICE 許諾番号07RB0167 | |||||||||
| 著者版フラグ | ||||||||||
| 出版タイプ | VoR | |||||||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||||||
| 関連URI | ||||||||||
| 識別子タイプ | URI | |||||||||
| 関連識別子 | http://search.ieice.org/ | |||||||||
