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A 0.3-V operating, Vth-variation-tolerant SRAM under DVS environment for memory-rich SoC in 90-nm technology era and beyond
http://hdl.handle.net/2297/7538
http://hdl.handle.net/2297/7538381c9576-96be-4a7e-ac08-613ac65d5460
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
TE-PR-MORITA-Y-060801.pdf (511.1 kB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2017-10-03 | |||||
| タイトル | ||||||
| タイトル | A 0.3-V operating, Vth-variation-tolerant SRAM under DVS environment for memory-rich SoC in 90-nm technology era and beyond | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | journal article | |||||
| 著者 |
Morita, Yasuhiro
× Morita, Yasuhiro× Fujiwara, Hidehiro× Noguchi, Hiroki× Kawakami, Kentaro× Miyakoshi, Junichi× Mikami, Shinji× Nii, Koji× Kawaguchi, Hiroshi× Yoshimoto, Masahiko |
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| 提供者所属 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | 元・大学院自然科学研究科 | |||||
| 提供者所属 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | 現・神戸大学大学院自然科学研究科 | |||||
| 書誌情報 |
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 巻 E89-A, 号 12, p. 3634-3641, 発行日 2006-12-01 |
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| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 0916-8508 | |||||
| NCID | ||||||
| 収録物識別子タイプ | NCID | |||||
| 収録物識別子 | AA10826239 | |||||
| DOI | ||||||
| 関連タイプ | isVersionOf | |||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | 10.1093/ietfec/e89-a.12.3634 | |||||
| 出版者 | ||||||
| 出版者 | Oxford University Press | |||||
| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | We propose a voltage control scheme for 6T SRAM cells that makes a minimum operation voltage down to 0.3 V under DVS environment. A supply voltage to the memory cells and wordline drivers, bitline voltage, and body bias voltage of load pMOSFETs are controlled according to read and write operations, which secures operation margins even at a low operation voltage. A self-aligned timing control with a dummy wordline and its feedback is also introduced to guarantee stable operation in a wide range of the supply voltage. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that a power reduction of 30 can be achieved at 100 MHz. In a 65-nm 64-Mb SRAM, a 74 power saving is expected at 1/6 of the maximum operating frequency. The performance penalty by the proposed scheme is less than 1, and area overhead is 5.6. Copyright © 2006 The Institute of Electronics, Information and Communication Engineers. | |||||
| 著者版フラグ | ||||||
| 出版タイプ | AM | |||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
