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An adaptive SC line equalizer system for four-wire full-duplex and multirate digital transmission
http://hdl.handle.net/2297/3944
http://hdl.handle.net/2297/39447ad7f789-0978-4aab-b717-590bccedd210
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
TE-PR-NAKAYAMA-K-1073.pdf (663.3 kB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||
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| 公開日 | 2017-10-03 | |||||
| タイトル | ||||||
| タイトル | An adaptive SC line equalizer system for four-wire full-duplex and multirate digital transmission | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | journal article | |||||
| 著者 |
Nakayama, Kenji
× Nakayama, Kenji× Takahashi, Yutaka× Sato, Yayoi× Nukada, Yasuaki |
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| 提供者所属 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | 金沢大学大学院自然科学研究科情報システム | |||||
| 提供者所属 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | 金沢大学工学部 | |||||
| 書誌情報 |
IEEE Trans. Circuits and Systems 巻 35, 号 9, p. 1073-1081, 発行日 1988-09-01 |
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| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 0098-4094 | |||||
| DOI | ||||||
| 関連タイプ | isIdenticalTo | |||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | https://doi.org/10.1109/31.7566 | |||||
| 出版者 | ||||||
| 出版者 | IEEE | |||||
| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | An adaptive switched-capacitor (SC) line equalizer system that can be applied to four-wire full-duplex and multirate digital transmission is described. Several kinds of noises can exist in programmable high-gain SC equalizers, such as switching noise, DC offset jump, and transient response. To avoid their effects, an adaptive SC filter is proposed. Two identical SC circuits are used in parallel. An input signal is fed into both SC circuits, and output signals from both circuits are alternately sent after the above noises are eliminated. Furthermore, many different data rates can be handled by slightly modifying an equalizer circuit. A bridged-tap echo canceller and a DC offset canceller are modified so as to be applied to the proposed adaptive SC filter. A line equalizer system, that handles data rates ranging from 3.2 to 64 kb/s was designed. An LSI was fabricated using a 3-μm CMOS process. Experimental results show that noise effects are mostly eliminated, and frequency responses and eye openings are close to the designed values. | |||||
| 著者版フラグ | ||||||
| 出版タイプ | VoR | |||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
