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A VLSI architecture for VGA 30 fps video segmentation with affine motion model estimation
https://doi.org/10.24517/00008074
https://doi.org/10.24517/00008074a06a816c-7ffa-472c-a2f8-3251d318f6de
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
TE-PR-MIYAMA-M-449.pdf (599.1 kB)
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| Item type | 会議発表論文 / Conference Paper(1) | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 公開日 | 2017-10-03 | |||||||||
| タイトル | ||||||||||
| タイトル | A VLSI architecture for VGA 30 fps video segmentation with affine motion model estimation | |||||||||
| 言語 | ||||||||||
| 言語 | eng | |||||||||
| 資源タイプ | ||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||||||
| 資源タイプ | conference paper | |||||||||
| ID登録 | ||||||||||
| ID登録 | 10.24517/00008074 | |||||||||
| ID登録タイプ | JaLC | |||||||||
| 著者 |
Miyama, Masayuki
× Miyama, Masayuki× Yunbe, Yoshiki× Togo, Kouji× Matsuda, Yoshio |
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| 著者別表示 |
深山, 正幸
× 深山, 正幸
× 松田, 吉雄
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| 提供者所属 | ||||||||||
| 内容記述タイプ | Other | |||||||||
| 内容記述 | 金沢大学理工研究域電子情報学系 | |||||||||
| 書誌情報 |
ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings 号 5403917, p. 449-452, 発行日 2009-01-01 |
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| 出版者 | ||||||||||
| 出版者 | IEEE = Institute of Electrical and Electronics Engineers | |||||||||
| 抄録 | ||||||||||
| 内容記述タイプ | Abstract | |||||||||
| 内容記述 | This paper proposes a VLSI architecture for VGA 30 fps video segmentation with affine motion model estimation. The adopted algorithm is formulated as a contextual statistical labeling problem exploiting multiscale Markov random field (MRF) models. The algorithm optimization for VLSI implementation is characterized by image division method, ICM labeling limited to region boundary, and omission of motion models estimation for new regions. The optimization reduces the computational costs by 82 %, the amount of memory by 95 %, and the amount of data traffic by 99 % without accuracy degradation. The VLSI architecture is characterized by pipeline processing of the divided images, concurrent motion models estimation for multiple regions, and a common processing element of update and detection labeling. The architecture enables VGA 30 fps video segmentation with 167 MHz frequency. The estimated core area using 0.18μm technology is 30 mm2. This processor is applicable to the video recognition applications such as vehicle safety, robot, and surveillance systems under the restriction of energy consumption. | |||||||||
| 著者版フラグ | ||||||||||
| 出版タイプ | VoR | |||||||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||||||
