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Accelerated evaluation method for the SRAM cell write margin using word line voltage shift
https://doi.org/10.24517/00008566
https://doi.org/10.24517/00008566b944b934-96fc-479f-8a8d-3e00c212472b
| 名前 / ファイル | ライセンス | アクション |
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TE-PR-MATSUDA-Y-63.pdf (302.8 kB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||||||
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| 公開日 | 2017-10-03 | |||||||||
| タイトル | ||||||||||
| タイトル | Accelerated evaluation method for the SRAM cell write margin using word line voltage shift | |||||||||
| 言語 | ||||||||||
| 言語 | eng | |||||||||
| 資源タイプ | ||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||||
| 資源タイプ | journal article | |||||||||
| ID登録 | ||||||||||
| ID登録 | 10.24517/00008566 | |||||||||
| ID登録タイプ | JaLC | |||||||||
| 著者 |
Makino, Hiroshi
× Makino, Hiroshi× Nakata, Shunji× Suzuki, Hirotsugu× Morimura, Hiroki× Mutoh, Shin'ichiro× Miyama, Masayuki× Yoshimura, Tsutomu× Iwade, Shuhei× Matsuda, Yoshio |
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| 著者別表示 |
深山, 正幸
× 深山, 正幸
× 松田, 吉雄
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| 書誌情報 |
2011 International Symposium on Integrated Circuits 巻 ISIC 2011, 号 6131880, p. 63-66, 発行日 2011-01-01 |
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| DOI | ||||||||||
| 関連タイプ | isVersionOf | |||||||||
| 識別子タイプ | DOI | |||||||||
| 関連識別子 | 10.1109/ISICir.2011.6131880 | |||||||||
| 出版者 | ||||||||||
| 出版者 | IEEE | |||||||||
| 抄録 | ||||||||||
| 内容記述タイプ | Abstract | |||||||||
| 内容記述 | An accelerated evaluation method for the SRAM cell write margin is proposed based on the conventional Write Noise Margin (WNM) definition. The WNM is measured under a lower word line voltage than the power supply voltage VDD. A lower word line voltage is used because the access transistor operates in the saturation mode over a wide range of threshold voltage variation. The final WNM at the VDD word line voltage, the Accelerated Write Noise Margin (AWNM), is obtained by shifting the measured WNM at the lower word line voltage. The amount of WNM shift is determined from the WNM dependence on the word line voltage. As a result, the cumulative frequency of the AWNM displays a normal distribution. A normal distribution of the AWNM drastically improves development efficiency, because the write failure probability can be estimated by a small number of samples. Effectiveness of the proposed method is verified using the Monte Carlo simulation. © 2011 IEEE. | |||||||||
| 著者版フラグ | ||||||||||
| 出版タイプ | AM | |||||||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||||||
