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Pulse number control of electrical resistance for multi-level storage based on phase change
https://doi.org/10.24517/00013164
https://doi.org/10.24517/00013164a3510917-531d-447f-af47-ad12cf16d8ed
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
ME-PR-NAKAYAMA-K-9.pdf (174.6 kB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||||||
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| 公開日 | 2017-10-03 | |||||||||
| タイトル | ||||||||||
| タイトル | Pulse number control of electrical resistance for multi-level storage based on phase change | |||||||||
| 言語 | ||||||||||
| 言語 | eng | |||||||||
| 資源タイプ | ||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||||
| 資源タイプ | journal article | |||||||||
| ID登録 | ||||||||||
| ID登録 | 10.24517/00013164 | |||||||||
| ID登録タイプ | JaLC | |||||||||
| 著者 |
Nakayama, Kazuya
× Nakayama, Kazuya× Takata, Masaki× Kasai, T.× Kitagawa, Akio× Akita, Junichi |
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| 著者別表示 |
中山, 和也
× 中山, 和也
× 秋田, 純一
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| 提供者所属 | ||||||||||
| 内容記述タイプ | Other | |||||||||
| 内容記述 | 金沢大学融合研究域融合科学系 | |||||||||
| 書誌情報 |
Journal of Physics D: Applied Physics 巻 40, 号 17, p. 5061-5065, 発行日 2007-09-07 |
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| ISSN | ||||||||||
| 収録物識別子タイプ | ISSN | |||||||||
| 収録物識別子 | 0022-3727 | |||||||||
| NCID | ||||||||||
| 収録物識別子タイプ | NCID | |||||||||
| 収録物識別子 | AA00704905 | |||||||||
| DOI | ||||||||||
| 関連タイプ | isVersionOf | |||||||||
| 識別子タイプ | DOI | |||||||||
| 関連識別子 | 10.1088/0022-3727/40/17/009 | |||||||||
| 出版者 | ||||||||||
| 出版者 | Institute of Physics | |||||||||
| 抄録 | ||||||||||
| 内容記述タイプ | Abstract | |||||||||
| 内容記述 | Phase change nonvolatile memory devices composed of SeSbTe chalcogenide semiconductor thin film were fabricated. The resistivity of the SeSbTe system was investigated to apply to multi-level data storage. The chalcogenide semiconductor acts as a programmable resistor that has a large dynamic range. The resistance of the chalcogenide semiconductor can be set to intermediate resistances between the amorphous and crystalline states using electric pulses of a specified power, and it can be controlled by repetition of the electric pulses. The size of the memory cell used in this work is 200 nm thick with a contact area of 1 µm diameter. The resistance of the chalcogenide semiconductor gradually varies from 41 kΩ to 840 Ω within octal steps. The resistance of the chalcogenide semiconductor decreases with increasing number of applied pulses. The step-down characteristic of the resistance can be explained as the crystalline region of the active phase change region increases with increasing number of applied pulses. The extent of crystallization was also estimated by the overall resistivity of the active region of the memory cell. | |||||||||
| 著者版フラグ | ||||||||||
| 出版タイプ | AM | |||||||||
| 出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||||||
| シリーズ | ||||||||||
| 関連名称 | 9 | |||||||||
