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A VGA 30fps affine motion model estimation VLSI for real-time video segmentation
https://doi.org/10.24517/00008161
https://doi.org/10.24517/000081618cd7df9c-30af-40b8-b7bb-0637a7947e6a
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
TE-PR-MIYAMA-M-3284.pdf (2.2 MB)
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| アイテムタイプ | 学術雑誌論文 / Journal Article(1) | |||||||||
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| 公開日 | 2017-10-03 | |||||||||
| タイトル | ||||||||||
| タイトル | A VGA 30fps affine motion model estimation VLSI for real-time video segmentation | |||||||||
| 言語 | ||||||||||
| 言語 | eng | |||||||||
| 資源タイプ | ||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||||||
| 資源タイプ | journal article | |||||||||
| ID登録 | ||||||||||
| ID登録 | 10.24517/00008161 | |||||||||
| ID登録タイプ | JaLC | |||||||||
| 著者 |
Yunbe, Yoshiki
× Yunbe, Yoshiki× Miyama, Masayuki× Matsuda, Yoshio |
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| 著者別表示 |
深山, 正幸
× 深山, 正幸
× 松田, 吉雄
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| 提供者所属 | ||||||||||
| 内容記述タイプ | Other | |||||||||
| 内容記述 | 金沢大学理工研究域電子情報学系 | |||||||||
| 書誌情報 |
IEICE Transactions on Information and Systems 巻 E93-D, 号 12, p. 3284-3293, 発行日 2010-12-01 |
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| ISSN | ||||||||||
| 収録物識別子タイプ | ISSN | |||||||||
| 収録物識別子 | 0916-8532 | |||||||||
| NCID | ||||||||||
| 収録物識別子タイプ | NCID | |||||||||
| 収録物識別子 | AA10826272 | |||||||||
| DOI | ||||||||||
| 関連タイプ | isIdenticalTo | |||||||||
| 識別子タイプ | DOI | |||||||||
| 関連識別子 | 10.1587/transinf.E93.D.3284 | |||||||||
| 出版者 | ||||||||||
| 出版者 | IEICE transactions on communications electronics information and systems = 電子情報通信学会 | |||||||||
| 抄録 | ||||||||||
| 内容記述タイプ | Abstract | |||||||||
| 内容記述 | This paper describes an affine motion estimation processor for real-time video segmentation. The processor estimates the dominant motion of a target region with affine parameters. The processor is based on the Pseudo-M-estimator algorithm. Introduction of an image division method and a binary weight method to the original algorithm reduces data traffic and hardware costs. A pixel sampling method is proposed that reduces the clock frequency by 50%. The pixel pipeline architecture and a frame overlap method double throughput. The processor was prototyped on an FPGA; its function and performance were subsequently verified. It was also implemented as an ASIC. The core size is 5.0 × 5.0 mm2 in 0.18 μm process, standard cell technology. The ASIC can accommodate a VGA 30 fps video with 120 MHz clock frequency. Copyright© 2010. | |||||||||
| 権利 | ||||||||||
| 権利情報 | Copyright (c) 2010 The Institute of Electronics, Information and Communication Engineers | |||||||||
| 著者版フラグ | ||||||||||
| 出版タイプ | VoR | |||||||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||||||
| 関連URI | ||||||||||
| 識別子タイプ | URI | |||||||||
| 関連識別子 | http://www.jstage.jst.go.jp/article/transinf/E93.D/12/E93.D_3284/_article | |||||||||
