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Adiabatic SRAM with a large margin of VT variation by controlling the cell-power-line and word-line voltage
https://doi.org/10.24517/00009798
https://doi.org/10.24517/00009798f8e14af9-22dd-4464-a88f-9d3fea11c2ef
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
TE-PR-MATSUDA-Y-393.pdf (905.2 kB)
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| Item type | 会議発表論文 / Conference Paper(1) | |||||||||
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| 公開日 | 2017-10-03 | |||||||||
| タイトル | ||||||||||
| タイトル | Adiabatic SRAM with a large margin of VT variation by controlling the cell-power-line and word-line voltage | |||||||||
| 言語 | ||||||||||
| 言語 | eng | |||||||||
| 資源タイプ | ||||||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||||||
| 資源タイプ | conference paper | |||||||||
| ID登録 | ||||||||||
| ID登録 | 10.24517/00009798 | |||||||||
| ID登録タイプ | JaLC | |||||||||
| 著者 |
Nakata, S.
× Nakata, S.× Kusumoto, Takahito× Miyama, Masayuki× Matsuda, Yoshio |
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| 著者別表示 |
深山, 正幸
× 深山, 正幸
× 松田, 吉雄
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| 提供者所属 | ||||||||||
| 内容記述タイプ | Other | |||||||||
| 内容記述 | 金沢大学理工研究域電子情報学系 | |||||||||
| 書誌情報 |
Proceedings - IEEE International Symposium on Circuits and Systems 巻 2009, p. 393-396, 発行日 2009-01-01 |
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| ISSN | ||||||||||
| 収録物識別子タイプ | ISSN | |||||||||
| 収録物識別子 | 0271-4310 | |||||||||
| DOI | ||||||||||
| 関連タイプ | isIdenticalTo | |||||||||
| 識別子タイプ | DOI | |||||||||
| 関連識別子 | 10.1109/ISCAS.2009.5117768 | |||||||||
| 出版者 | ||||||||||
| 出版者 | IEEE = Institute of Electrical and Electronics Engineers | |||||||||
| 抄録 | ||||||||||
| 内容記述タイプ | Abstract | |||||||||
| 内容記述 | An adiabatic 1-kb SRAM circuit was designed, which enables gradual charging during writing and reading while maintaining a large VDD so that the problems of VT variation and electromigration in the nanocircuit can be resolved. In the writing mode, the voltage of the memory cell power line is reduced to ground gradually using a high-resistivity nMOSFET, and we turn off the nMOSFET so that the memory cell power line is set in a high-impedance state. Then, we can write data easily by inputting adiabatic signal from one bit line, while the other bit line is set to ground. For reading, a verifying operation is proposed for resolving the electromigration problem. The word line voltage is changed stepwise while the voltages of the bit lines are verified. The reading method enables a gradual current flow in the memory cell. We designed the cell layout and found that there is no area penalty. In addition, a new charge recycle circuit with tank capacitors is proposed. ©2009 IEEE. | |||||||||
| 著者版フラグ | ||||||||||
| 出版タイプ | VoR | |||||||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||||||
| シリーズ | ||||||||||
| 関連名称 | 5117768 | |||||||||
