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A multiplier-less digital timing extractor circuit with round-off error canceller
http://hdl.handle.net/2297/6837
http://hdl.handle.net/2297/68378eb4f890-d8b4-4769-9105-6da62ec24dcf
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
TE-PR-NAKAYAMA-K-1483.pdf (468.7 kB)
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| Item type | 会議発表論文 / Conference Paper(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2017-10-03 | |||||
| タイトル | ||||||
| タイトル | A multiplier-less digital timing extractor circuit with round-off error canceller | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||
| 資源タイプ | conference paper | |||||
| 著者 |
Nakayama, Kenji
× Nakayama, Kenji× Kuriki, Satoshi |
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| 書誌情報 |
Proceedings - IEEE International Symposium on Circuits and Systems p. 1483-1486, 発行日 1985-06-01 |
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| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 0271-4310 | |||||
| 出版者 | ||||||
| 出版者 | IEEE(Institute of Electrical and Electronics Engineers) | |||||
| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | A simplified digital tuned-circuit extractor is proposed. An A/D converter and multipliers are not required. An A/D converter and multipliers are not required. The tuning frequency is determined only by a master clock. The tank circuit output noise is sufficiently suppressed by newly introduced error canceller. Although sampling frequency for the tank circuit is relatively low, the phase of the output signal is effectively detected. A computer simulation shows that phase adjusting for data sampling clock is stable. The proposed timing extractor is easily realized on digital integrated circuits. | |||||
| 著者版フラグ | ||||||
| 出版タイプ | VoR | |||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
